Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a circuit for delaying an input clock in a semiconductor device.
In general, data is to be inputted/outputted in synchronization with a reference clock in a synchronous semiconductor memory device such as a double data rate synchronous dynamic random access memory (DDR SDRAM) device.
Here, since the reference clock mainly represents an external clock CLK/CLKB inputted from an external device such as a memory controller, in order to transmit data that are time-synchronized with the reference clock, the synchronous semiconductor memory device is desired to output the data accurately at the edge or the center of a pulse of the external clock CLK/CLKB.
However, The external clock CLK/CLKB that is inputted into the semiconductor memory device are buffered through an input buffering circuit and used as an internal clock, and the phase of the internal clock is changed as the internal clock passes through all internal circuits (e.g., control circuits, peripheral circuits, and a cell array) of the semiconductor memory device. When the internal clock is transferred and used in an output buffering circuit, the internal clock may be asynchronous with the external clock CLK/CLKB.
At this time, if data are outputted from the semiconductor memory device in synchronization with the internal clock, the data may be outputted from the semiconductor memory device in non-synchronization with the external clock CLK/CLKB due to the phase difference between the internal clock and the external clock CLK/CLKB.
Therefore, in order to output data in time-synchronization with the phase of the external clock CLK/CLKB that is a reference clock in the semiconductor memory device, a delay time, by which the internal clock is delayed until the internal clock generated from the external clock CLK/CLKB is transmitted to an output pad is to be reversely compensated to the internal clock applied to the output pad to make the phase of the internal clock be synchronized with the phase of the external clock CLK/CLKB.
Typical examples of the circuit for synchronizing the phase of the internal clock with the phase of the external clock CLK/CLKB by compensating the time by which the phase of the internal clock is delayed as described above are a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit.
The PLL circuit is mainly used to simultaneously synchronize a frequency and a phase of the internal clock with those of the external clock using a frequency multiplication function when the frequency of the internal clock used in the semiconductor memory device becomes different from the frequency of the external clock inputted from an external device as a reference clock.
On the other hand, the DLL circuit is used to synchronize only a phase of the internal clock with that of the external clock when the frequency of the internal clock is the same as that of the external clock.
Although the PLL circuit has an additional function such as the frequency multiplication function compared to the DLL circuit as described above, the DLL circuit is practically used more widely than the PLL circuit in case of the semiconductor memory device. There are various reasons therefor. The representative reason is that the DLL circuit may be less sensitive about noise and occupy a smaller area than the PLL circuit.
FIG. 1 is a block diagram illustrating a delay locked loop circuit provided in a general semiconductor device.
Referring to FIG. 1, a delay locked loop (DLL) circuit provided in a general semiconductor device includes: a phase comparing unit 100R/100F configured to compare the phase of a source clock REFCLK with the phase of a feedback clock FBCLKR/FBCLKF; a control pulse generating unit 110 configured to generate a plurality of control pulses PULSE2, PULSE3, and PULSE6 activated sequentially for delay shifting update periods in response to a control clock CONTCLK; a mode controlling unit 160R/160F configured to generate mode control signals FM_END, LOCK_STATE, FM_END_F, and LOCK_STATEF corresponding to the comparison results FINE, COARSE, FM_PDOUT, FINEF, COARSEF, and FM_PDOUTF of the phase comparing unit 100R/100F; a delay shift controlling unit 130R/130F configured to generate first delay shift control signals FRCLK_SL, FRCLK_SR, SRCLK_SL, SRCLK_SR, FFCLK_SL, FFCLK_SR, SFCLK_SL, and SFCLK_SR for controlling a delay shifting operation in a normal mode and a coarse mode and second delay shift control signals FASTR_SL and FASTF_SL for controlling the delay shifting operation in a fast mode in response to the mode control signals FM_END, LOCK_STATE, FM_END_F, and LOCK_STATEF; a phase delaying unit 140R/140F configured to delay-shift the phases of internal clocks CLKIN1 and CLKIN2 on a delay unit basis in response to the first delay shift control signals FRCLK_SL, FRCLK_SR, SRCLK_SL, SRCLK_SR, FFCLK_SL, FFCLK_SR, SFCLK_SL, and SFCLK_SR in the normal mode, delay-shift the phases of the internal clocks CLKIN1 and CLKIN2 on a unit (smaller than the delay unit) basis in response to the first delay shift control signals FRCLK_SL, FRCLK_SR, SRCLK_SL, SRCLK_SR, FFCLK_SL, FFCLK_SR, SFCLK_SL, and SFCLK_SR in the coarse mode, and delay-shift the phases of the internal clocks CLKIN1 and CLKIN2 on a delay group (including a plurality of delay units) basis in response to the second delay shift control signals FASTR_SL and FASTF_SL in the fast mode; a delay duplication modeling unit 150R/150F configured to delay an output clock IFBCLKR/IFBCLKF of a duty correcting unit 120 using a delay time in which the actual delay conditions of an internal clock path are reflected and output the feedback clock FBCLKR/FBCLKF; a clock buffering unit 180B configured to buffer an external clock CLK and generate the source clock REFCLK, control clock CONTCLK, and internal clocks CLKIN1 and CLKIN2, the phases of which are synchronized; a power-down mode controlling unit 180A configured to generate a clock buffer enable signal CLKBUF_ENB for controlling an operation of the clock buffering unit 180B in response to an inversion signal CKEB_COM of a clock enable signal, a signal SAPD with power-down mode information of a mode register set MRS, and a signal RASIDLE with precharge information; a DLL controlling unit 190 configured to generate a reset signal RESET for controlling an operation of the DLL circuit in response to a DLL disable signal DIS_DLL and a DLL reset signal DLL_RESETB inputted from an external device of a semiconductor memory device; a pre duty correcting unit 119 configured to invert the phase of the output clock MIXOUT_R/MIXOUT_F (mainly MIXOUT_F) of the phase delay unit 140R/140F and output a rising internal clock RISING_CLK with a rising edge corresponding to the rising edge of the internal clocks CLKIN1 and CLKIN2 and a falling internal clock FALLING_CLK with a rising edge corresponding to the falling edge of the internal clocks CLKIN1 and CLKIN2; the duty correcting unit 120 configured to correct the duty cycle ratio of the output clocks RISING_CLK and FALLING_CLK of the pre duty correcting unit 119 in a locking state; and a DLL driver 170 configured to output DLL output clocks IRCLKDLL and IFCLKDLL, generated by driving the output clocks IFBCLKR and IFBCLKF of the duty correcting unit 120, to an output driver of the semiconductor memory device.
Hereinafter, an operation of the conventional DLL circuit will be described with reference to the configuration thereof.
The aforesaid register-controlled DLL circuit is a DLL circuit that operates in a dual-loop mode. The DLL circuit in the dual-loop mode performs a DLL operation by means of two clocks with opposite phases and performs a duty cycle ratio correction operation to make the duty cycle ratio of the final output clock be 50:50 when it becomes a locking state through the DLL operation.
That is, the DLL circuit in the dual-loop mode performs a DLL operation by using the rising internal clock RISING_CLK with a rising edge corresponding to the rising edge of the internal clocks CLKIN1 and CLKIN2 and the falling internal clock FALLING_CLK with a rising edge corresponding to the falling edge of the internal clocks CLKIN1 and CLKIN2.
Meanwhile, there is a single-loop mode that is contrary to the dual-loop mode. The DLL circuit in the single-loop mode performs a DLL operation by means of only one clock corresponding to the rising edge or the falling edge of the internal clocks CLKIN1 and CLKIN2 before performing a duty cycle ratio correction operation, and performs a duty cycle ratio correction operation when it becomes a locking state through the DLL operation.
Among the components of the CLL circuit, the mode controlling unit 160R/160F, the phase comparing unit 100R/100F, the delay shift controlling unit 130R/130F, the phase delaying unit 140R/140F, and the delay duplication modeling unit 150R/150F may be divided into the blocks 100R, 160R, 130R, 140R, and 150R for controlling the phase of the rising internal clock RISING_CLK and the blocks 100F, 160F, 130F, 140F, and 150F for controlling the phase of the falling internal clock FALLING_CLK, which have the same circuit configurations, respectively.
Here, the blocks 100R, 160R, 130R, 140R, and 150R control the phase of the rising internal clock RISING_CLK for the rising edge of the rising internal clock RISING_CLK to be synchronized with the rising edge of the source clock REFCLK, before the locking state and even after the locking state. This is to make a locking state before the locking state, and to compensate for the phase shift of the rising clock RISING_CLK due to the influence of the noise or the power supply voltage applied from an external device of the semiconductor device after the locking state.
The blocks 100F, 160F, 130F, 140F, and 150F controls the phase of the falling internal clock FALLING_CLK for the rising edge of the rising internal clock RISING_CLK to be synchronized with the rising edge of the source clock REFCLK before the locking state. After the locking state, only some (130F and 140F) of the blocks 100F, 160F, 130F, 140F, and 150F operate and the other blocks 100F, 160F, and 150F do not operate. This is to make a locking state before the locking state and to prevent the output of the DLL circuit driver 170 from being affected by the phase shift of the falling internal clock FALLING_CLK after the locking state.
For reference, in a general dual-mode register-controlled DLL circuit, the locking state means the state where the rising edge of the source clock REFCLK, the rising edge of the rising internal clock RISING_CLK, and the rising edge of the falling internal clock FALLING_CLK are all synchronized within a predetermined margin of error.
FIG. 2 is a circuit diagram illustrating a conventional phase delaying unit of the delay locked loop circuit provided in the general semiconductor device illustrated in FIG. 1.
For reference, FIG. 2 illustrates the first phase delaying unit 140R of the phase delaying unit (140R/140F) in detail. Except the difference in the names of input/output signals, the detailed circuit configuration of the second phase delaying unit 140F is identical to the detailed circuit configuration of the first phase delaying unit 140R.
Referring to FIG. 2, the conventional phase delaying unit 140R of the delay locked loop circuit included in the conventional semiconductor device illustrated in FIG. 1 includes a delay line 1402R and a delay line controlling unit 1404R. The delay line 1402R is configured to delay a source clock REFCLK to generate a delay locked clock MIXOUT_R, wherein a delay amount of the delay line 1402R changes on a delay unit basis in response to a delay control code DELAY_CONT<1:N>. The delay line controlling unit 1404R is configured to generate the delay control code DELAY_CONT<1:N> in response to the first and second delay shift control signals FRCLK_SL, FRCLK_SR, SRCLK_SL, SRCLK_SR, and FASTR_SL received from the first delay shift controlling unit 130R.
Here, the delay line 1402R includes a plurality of delay units UNIT DELAY<1:N> and a delay controlling unit 14022R. The delay units UNIT DELAY<1:N> are connected in series. The delay controlling unit 14022R is configured to provide the source clock REFCLK to any one of the delay units UNIT DELAY<1:N> in response to the delay control code DELAY_CONT<1:N>.
Hereinafter, an operation of the first phase delaying unit 140R in the conventional DLL circuit will be described with reference to the configuration thereof.
When the delay amount of the delay line 1402R is determined to be increased according to the first and second delay shift control signals FRCLK_SL, FRCLK_SR, SRCLK_SL, SRCLK_SR, and FASTR_SL received from the first delay shift controlling unit 130R, the delay line controlling unit 1404R increases the value of the delay control code DELAY_CONT<1:N> and the number of delay units, through which the source clock REFCLK passes among the delay units UNIT DELAY<1:N> in the delay line 1402R, is increased accordingly, thus increasing the delay amount thereof.
For example, it is assumed that the delay control code DELAY_CONT<1:N> is an 8-bit signal DELAY_CONT<1:8> and the current value is ‘0 0 0 1 0 0 0 0’. In this case, if the delay amount of the delay line 1402R is determined to be increased by the first and second delay shift control signals FRCLK_SL, FRCLK_SR, SRCLK_SL, SRCLK_SR, and FASTR_SL, the value of the delay control code DELAY_CONT<1:N> may be increased to be ‘0 0 1 0 0 0 0 0’, ‘0 1 0 0 0 0 0 0’, and ‘1 0 0 0 0 0 0 0’, sequentially. Accordingly, the number of delay lines, through which the source clock REFCLK passes among the delay units UNIT DELAY<1:N> in the delay line 1402R, is increased from 5 to 6, 7, and 8, sequentially, thus increasing the delay amount thereof.
On the other hand, when the delay amount of the delay line 1402R is determined to be decreased according to the first and second delay shift control signals FRCLK_SL, FRCLK_SR, SRCLK_SL, SRCLK_SR, and FASTR_SL received from the first delay shift controlling unit 130R, the delay line controlling unit 1404R decreases the value of the delay control code DELAY_CONT<1:N> and the number of delay lines, through which the source clock REFCLK passes among the delay units UNIT DELAY<1:N> in the delay line 1402R, is decreased accordingly, thus decreasing the delay amount thereof.
For example, it is assumed that the delay control code DELAY_CONT<1:N> is an 8-bit signal DELAY_CONT<1:8> and the current value is ‘0 0 0 1 0 0 0 0’. In this case, if the delay amount of the delay line 1402R is determined to be decreased by the first and second delay shift control signals FRCLK_SL, FRCLK_SR, SRCLK_SL, SRCLK_SR, and FASTR_SL, the value of the delay control code DELAY_CONT<1:N> may be decreased to become ‘0 0 0 0 1 0 0 0’, ‘0 0 0 0 0 1 0 0’, ‘0 0 0 0 0 0 1 0’, and ‘0 0 0 0 0 0 0 1’, sequentially. Accordingly, the number of delay lines, through which the source clock REFCLK passes among the delay units UNIT DELAY<1:N> in the delay line 1402R, is decreased from 5 to 4, 3, 2, and 1, sequentially, thus decreasing the delay amount thereof.
However, in the configuration of the first phase delaying unit 140R of the general DLL circuit in the semiconductor device, a maximum delay amount thereof is predetermined, and a DLL operation fail may occur if the locking operation of the DLL circuit cannot be completed even using all of the delay amount.
Therefore, in the configuration of the first phase delaying unit 140R of the conventional DLL circuit in the semiconductor device, it is important to determine the degree of the predetermined delay amount.
The reason for this is that if the delay amount is determined to be too small, a DLL operation fail may occur, thus causing the malfunction of the semiconductor device.
On the other hand, if the delay amount is determined to be too large, it occupies a large area and causes much jitter in the delay locked clock MIXOUT_R, thus increasing the probability that other internal circuits using the delay locked clock MIXOUT_R may perform abnormal operations.